Essential VHDL

Errata for Essential VHDL

Note: Errata that are numbered in black only apply to books from the first printing. Those numbered in red apply to both the first and second printing. To determine whether you have a book from the first or second printing, open the very first page of the book, that faces the Contents page. There, you should find the printing history. "Second Article, March 1999" indicates that your book came from the second printing.

Chapter 1
1.1 The first few paragraphs of the section titled Connecting Logic Using Signals on page 2 might be a little confusing. The last three paragraphs on page 2 should read:

In "real" hardware, signals can be thought of as wires. In a more abstract sense, they are analagous to data queues. This is because new values assigned to signals may be queued in time order and "scheduled" at a particular time, from 0ns to the largest time value supported by your VHDL simulator. This abstract model leads to some important properties of signals, which we will discuss later on in the book, most notably in Chapter 8.
Every signal has a type. A type is a collection of values that a signal can take. VHDL inherently supports a type known as bit, which allows signals of this (bit) type to take the values '0' or '1'. Additionally, VHDL natively supports the integer type, where signals of this type may take integer values between +(231 - 1) to -(231 -1).
However, wires in real hardware take on values other than the '0' or '1'. We might see the high-impedance value, 'Z', or perhaps we might wish to model an unknown value, 'X'. As such, you will most often use the std_logic type,defined in the IEEE 1164 standard, when describing wires as signals. The std_logic type has nine values. These values are as shown in Table 1.

Chapter 3
3.1 One page 28, the fourth line in the paragraph that immediately follows Figure 4 should read as follows:

want to explicitly...

Chapter 4
4.1 The second to last paragraph of page 73 should read as follows:

There is an important observation to make when creating latches using a process and if…then statement. Notice that the latch is created by the if…then statement without a closing else. The latch is implied or inferred from the lack of the closing else prior to the end if. This can lead to significant consequences on the logic generated if the else is omitted "accidentally", as we will see in Chapter 8.

4.2 The word async on page 63 (4th line of the first paragraph) should read arst.

Chapter 5
5.1 The design.vhd example (Listing 14) on page 97 has two small bugs, as a result of which the design will not follow the description written on page 96. This has now been corrected. Correspondingly, Figure 8 on page 96 also changes slightly.

5.2 The equal1.vhd example (Listing 9) on page 90 uses the std_logic_unsigned package. It should use the numeric_std package, as indicated in the correction.

5.3 On page 76, The second paragraph indicates that numeric_std package defines signed and unsigned as subtypes of std_logic. This is incorrect. Both signed and unsigned types are defined as unconstrained arrays of type std_logic.

5.4 The to_stdlogicvector type conversion function was removed from the final version of the numeric_std package. As such, not all synthesis or simulation tools will support this function. Type conversion in Chapter 5 can be performed without the use of such a function. Paragraphs 3 on page 76 should read as follows:

Numeric_std defines two unconstrained arrays of std_logic known as signed and unsigned, which ....... in your designs. In the event that your design is hierarchical, this would require using the unsigned type throughout your design, or performing a type conversion at the port level. To illustrate this, let us consider the design of a counter.

Paragraph 1 on page 77 should be modified as follows:
..... . Hence the need to use countL, followed by a concurrent assignment with the type conversion to equate the count to countL. The type conversion can be performed in this way, since the two types are very similar (signed and unsigned types are arrays of std_logic). Notice also that there is no else condition that...... .

This errata changes the following examples:

Chapter 5: Listing 1, Listing 2, Listing 3, Listing 4, Listing 5, Listing 6, Listing 7, Listing 8, Listing 10, Listing 11, Listing 13 and Listing 14.

Chapter 12: Listing 4, Listing 5, Listing 7.

Chapter 13: Listing 2, Listing 3, Listing 8.

5.5 Listing 1 on page 76 should be titled Simple Up-counter, and not Counter Using a Wait Statement.

5.6 Listing 10 on page 91 should be titled Use of to_unsigned Function, and not Use of to_stdlogicvector Function.

5.7 Listing 1 on page 91 should be titled Simple up-counter. Correspondingly, the entry on page xvifor Chapter 5, Listing 1 should also read Simple up-counter.

5.8 The first line of the code example at the bottom of page 87 should read as follows:

if (a >= b) then

Chapter 6
6.1 This errata is superceeded by Errata 6.2.

6.2 Listing 10, pulsefsm.vhd, on page 118 does not indicate the complete listing for the pulse generator design.

6.3 In a state machine, outputs may also condition the next state value (as demonstrated by the PCI state machine developed in this chapter). As such, Figure 1 on page 102 should be modified slightly to reflect this.

6.4 Figure 5 on page 115 has a small ommision. The state waitDelayEnd transitions to loadDelayCnt if condition C1 is asserted. This has been corrected.

Chapter 7
7.1 The line that precedes Listing 5 on page 130 should read:

The listing for this counter, excluding the enable signal, is shown in Listing 5 and the logic generated by this counter is shown in Listing 7.
Also, Figure 5 and Figure 6 on page 130 have been updated so that their port names match the VHDL in Listing 5.

7.2 Listing 7 on page 133 is oeconc.vhd and not oecond.vhd.

Chapter 9
9.1 Figure 2, on page 168, has a minor error. The two blocks labelled I/O Sequencer should be labelled I/O Interface, as indicated in Figure 1. This has been corrected.

9.2 The very first library declaration and use clause in Listing 3 on page 177 is unnecessary. While it does not harm, and will certainly compile without any harm to the rest of the design, it is not required and can be eliminated.

9.3 The title of Listing 8 on page 183 should have the keywords for all in italics.

9.4 The comment in Listing 9, at the bottom of page 184 has a spelling error and should read as follows:

-- Configuration specifications

Chapter 10
10.1 Listing 6, on pages 204-207 does not declare default values for the state machine outputs. This results in implicit latch generation, which produces logically correct, though inefficient results. This has been corrected.

10.2 The state machine in Listing 6, on pages 204-207, will not be placed into a known state if it is reset while it is in operation. This is because the current state process,

simply sets
currState(Idle) <= '1'
without resetting the other bits in the state vector. This has been corrected.

Chapter 11
11.1 The first line, of the first paragraph on page 236 should as follows:

It is possible in VHDL to create logic conditionally. The conditions must be static, such as a .....

Chapter 12
12.1 Per Errata 5.4, Listing 1, on page 242 has been modified to demonstrate type conversion using the to_unsigned function. As a result, the first half of page 243 will change as follows:

Here we have used the function to_unsigned that is in the numeric_std package. While it would seem like the assignment

a <= Const

ought to work, it does not, since the types do not match. Hence the need to convert Const to an unsigned type.

Just like the operators we saw in Chapter 5, functions can be overloaded. For example, the to_unsigned function may be overloaded as follows:



We can call the function with either a non-negative integer (natural) or a std_logic_vector and the correct one will be picked, depending on the type of the argument passed. Most standard functions, like to_unsigned, accept unconstrained arrays as their inputs. In the case of a std_logic_vector argument, the result returned is of the same dimension and bit-ordering as the argument passed to it.

Chapter 13
13.1 The second paragraph of page 261 should read as follows:

This assignment using constants is required because VHDL is strongly typed. The value "0000100" might be a std_logic_vector, unsigned or string type, for example. Hence, the result type of the aggregate is ambiguous if it is assigned "0000100".

13.2 Figure 5 on page 270 has a small ommision. The state waitDelayEnd transitions to loadDelayCnt if condition C1 is asserted. This has been corrected.
Last updated: September 15, 1999